|SYMMIC Users Manual||CapeSym|
For a micro-scale device in a much larger integrated circuit, lateral heat spreading is the dominant mode of heat transfer away from the device. Therefore it is often important to include the entire chip in the thermal model of the device. This is can be done by creating a layout that describes the position of the device on the chip. There is considerable flexibility in how devices can be assembled in a layout to model an integrated circuit or subsystem, and this allows an enormous variety of models to be quickly generated from just a few basic templates. Adding device templates to a layout normally creates a valid thermal model, but there are a few special situations to avoid if Run simulation... will be used to solve the layout using superposition.
When analyzing a layout, it is important that all devices in a layout have a consistent set of common components, with identical layers and materials. This is because the solution to a layout is computed using a superposition of individual device solutions which assume that the common components are the same for all devices. Let's summarize this fact with the following caveat.
Do not solve layouts having devices with different common components, materials or layers.
Boundary conditions should likewise be consistent across all devices in a layout so that the solution can be correctly obtained through superposition. For each step in superposition, the designated boundary conditions of a single device are expanded to encompass the entire layout. For example, a layout with two FETs, one having a backside temperature of 300 K and the other having a backside temperature of 320 K would not superposition correctly. The same goes for differences in boundary conditions applied to the sides of the common layers of the devices.
Do not solve layouts having devices different backside boundary conditions.
Although it is possible to create a layout of devices that touch without any common layers, this will not produce a correct solution. If a device template is created from a layout without appending any common layers, then placing multiple copies of this device in a new layout will create this problem. Although the devices can be made to touch in the layout, they will be treated as independent (with adiabatic boundaries) in the thermal problem.
Do not solve layouts having devices without any common layers.
To participate in a valid layout, the features at the perimeter of the device must be composed exclusively of designated common components. There should be no features at the periphery that are not common to the entire layout. Any vias or special components that extend through the common layers underneath a device need to be contained within a perimeter of common components that are consistent with the other devices in the layout. This is true for basic device templates except at the mid-line of symmetrical transistor models.
For example, a layout containing a 2-gate half-FET device with source vias should not be placed in the middle of a layout without mirroring, because the source via feature is not designated as part of the layout's common components. The lack of validity of this layout is apparent in the solution mesh (see figure). In a multi-device layout the problem might not be evident in the mesh created to hold the final solution but would be still be present in the meshes used to perform the computation.
Placing an unmirrored half-device in the middle of a layout is not valid.
Do not place half-devices in the middle of a layout.
Mirroring a device along its mid-line usually eliminates the above problem. When a device is mirrored in a layout the entire perimeter is composed of only common components. This allows the device to be correctly expanded to the boundary during the superposition calculation.
Do not place half-devices in apposition at their mid-lines.
Two half-devices cannot be placed with mid-lines apposed to form a valid layout, in general, because there is no guarantee that the mesh of each half-device would be properly expanded. The above problem with half-devices in the middle of a layout is not fixed by putting two half-devices together.
In solving a layout of multiple devices by superposition, a primary assumption is that there are no features within a device that significantly affect heat spreading from adjacent devices. During a layout simulation, each device is solved independently, with feature-less common components placed at the locations of the other devices. The assumption (that devices do not significantly alter heat spreading in the common layers) is certainly valid when there are no vias or other such features in the devices. When common layer features are present in devices, the effect on heat spreading in the layout will depend on the materials used, the materials of the other common layers, and the distance between the devices.
Be wary of features that affect heat spreading between devices when solving a layout.
Note that the simulation of single device templates does not involve any limiting assumptions about heat spreading in common layers. A device template can be solved accurately regardless of the features it may contain because the superposition algorithm is not used. Layouts that cannot be solved accurately by superposition can be solved by creating an equivalent single device model. One way to do this is by using the Create device template... command, also known as “exporting” the layout. A high-resolution device template could also be created to solve the problem directly.
A large device model can sometimes be approximated by placing smaller devices close together, if a thin sliver of common components is maintained between them. For example, the figure below shows a 12-gate FET approximated by placing two 6-gate FETs side-by-side. The boundary distance of both devices was made as small as possible to enable the mirrored devices to be placed close together. The resulting peak junction temperature for the 2-device layout is within 0.5 °C of the peak for a similarly configured single device. In this case, all vias in the devices were filled with substrate material, supporting the assumption that there are no features affecting heat spreading in the common layers. Vias located at the junction of the two devices, if present, would likely affect heat spreading between the gates at the apposed ends, in which case a single device model would be more accurate.
Two adjacent FETs approximating a 12-gate device.
Be wary of passive devices in the layout.
Adding separate thermal vias as non-active devices in the layout might seem like a good way to remove heat, but in superposition simulations the passive devices may be removed from the model when simulating each active device. Likewise, passive bumps with top-side boundary conditions might not be included during superposition. The general rule is that superposition utilizes a single, uniform backside boundary condition for accurate superposition of the individual active devices.
Use belongsToMMIC when defining boundary conditions and components.
All boundary conditions and common components need to be properly designated in each device template by the “belongsToMMIC” attribute. Any boundary condition defined on a device that is not flagged in this manner will not be expanded to cover the entire layout during superposition. In general, device templates need to be designed to work together in a layout, with equivalent sets of boundary conditions and common components properly designated. The set of basic device templates installed with the software are designed to work together, but this might not be true for devices created in other ways. For example, a device created by exporting a layout cannot be combined with one of the devices from the original layout, because only the additional attached layers are marked as “belongsToMMIC” during export.
Given all of these caveats for defining a layout that can be solved by superposition, you may be asking yourself whether superposition could just be avoided altogether. Yes, it can. By using Create device template... on a layout to "export" the layout to a device template, the same problem can be solved without using superposition. This process is described in the next section, Creating Device Templates from Layouts. To solve a compound device, such as the two 6-gate FETs depicted above, the procedure described in Template Creation by Parts can be used to export the layout as a device template that accurately models a 12-gate FET. In this case it is allowable to place templates directly touching each other, and to have partial templates (i.e. without any border regions) in the layout. Also, in the resulting device template boundary conditions do not need to follow superposition rules, so any set of boundary conditions is permissible.
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