SYMMIC Users Manual CapeSym

A Generic FET Template

The generic FET template serves as a concrete example of a typical device, but different templates (with different parameters) may be required for thermal analysis of other FET technologies1. The generic FET template allows thermal analysis of a FET of up to 26 gates. The template models one half of a full FET, which is sufficient to fully characterize a symmetrical device. The half-device template can be configured to have from 1 to 13 gates, representing full FETs with 2 to 26 gates.



Top view of full FET device

The model is reconfigured based on the number of gates selected by the user. For odd numbers of gates in the template, the FET is divided along the center of the middle drain. For even numbers of gates in the template, the FET is divided along the center of the middle source. Source and drain lengths are individually modifiable, but the numbers present depend on the number of gates. A 1-gate model includes only Source#1 and half of Drain#1, a 2-gate model includes only Source#1, Drain#1 and half of Source#2, and so on.



Model of ¼ of a full FET

Note: Some components are optional and have to be “turned on” to be included in simulations. Examples are the Gate T Metal and the Source Bridge. Most components of the generic FET are always present, such as the layers and vias. But these components can often be effectively eliminated, if desired, by changing their materials to match those of adjacent components.



Layers

Backside Adhesive. The adhesive layer attaching shim to heat sink

Metal shim. The metal shim to which the device is soldered

Solder. The solder attaching the substrate to the metal shim

Substrate. The electrically insulating substrate

Epi-Layer 1 (bottom). The first semiconductor layer on top of the substrate

Epi-Layer 2 (middle). The middle layer of the active semiconductor layers

Epi-Layer 3 (top). The top layer of the active semiconductor layers

Ohmic Metal. The first metal layer forming source and drain contacts on the top epi-layer

Gate Metal. The gate metal contact on the top epi-layer

Drain Cap Metal. The metal on top of the drains and drain bus

Source Cap Metal. The metal on top of sources and source pad

Source Bridge Metal. The metal bridging sources and source pad. The presence of this metal is controlled through a parameter in the Pad/Bus/Boundary parameter list.

Gate T Metal. A layer of metal on top of the gate and gate bus. On the gate, the T metal starts at the source-side edge of the gate and extends to a point defined by the drain-side edge of the 4th power segment. Thus, length of the gate T metal can be specified by using the width of the 4th power segment. The presence of this metal is controlled through a parameter in the Finger/Channel/Gate list.



Source Lengths

1. Source Cap Length Offset. Difference between source and source cap metal lengths. Distance 1 in figure indicates ½ of total offset.

2. Source Length. Length of the contact between the source ohmic metal and the epi-layers

Drain Lengths

3. Drain Cap Length Offset. Difference between drain and drain cap metal lengths. Distance 3 in figure indicates ½ of total offset.

4. Drain Length. Length of the contact between the drain ohmic metal and the epi-layers

Pad/Bus/Boundary Dimensions

5. Drain Bus to Boundary. Distance from edge of drain bus to boundary of domain

6. Drain Bus to Source. Distance from edge of drain bus to ends of source fingers

7. Drain Bus Width. Width of the drain bus manifold

8. Gate Bus to Boundary. Distance from edge of gate bus to boundary of domain

9. Gate Bus to Source. Distance from edge of gate bus to the ends of source fingers

10. Gate Bus Width. Width of the gate bus manifold

11. Source Pad Length. Length of the source pad

12. Source Pad to Boundary. Distance from edge of source pad to boundary

Finger/Channel/Gate Dimensions

13. Finger Width. Widths of the epi-layers, sources, and drains

14. Gate Length. Length of the gate metal on the topmost epi-layer

15. Gate to Drain Distance. Distance from edge of gate to edge of drain contact

16. Gate to Source Distance. Distance from edge of gate to edge of source contact




Via Hole Dimensions

17. Source Pad Via Width. Width of source pad via hole

18. Source Pad Via Length. Length of the via hole under the source pad

19. Source Pad Via Metal. Thickness of the metal plating on the inside of the via hole

20. Source Via Width. Widths of the source via holes

21. Source Via Length. Length of the source via holes

22. Source Via Metal. Thickness of the metal plating on the inside of the source via holes

Note: Source via holes extend all the way through the epi-layers to contact the source metal.

Boundary Conditions

The power parameters set the surface flux in the heat generation region beneath the epi-layer. The Backside Film Temperature and the Backside Film Coefficient (a heat transfer coefficient for film, often called “h”,) set the film boundary condition at the bottom of the device. The heat transfer coefficient and temperature are intended to be used to capture the thermal resistance from the backside of the chip to the reference (e.g. cold plate) temperature. A very large value for the heat transfer coefficient (e.g. 1 W/um^2.°C) can be used to hold the backside temperature to a constant temperature. These parameters are modified in the Heat Generation parameters list.



Heating Profile

Heating in the epi-layer region is modeled as a sequence of intervals that divide the heat generation region into 4 segments. The width of each segment can be specified in the Heat Generation parameter dialog. A percentage of the total dissipated power is allocated to each segment. To accurately represent the total dissipated power, the segment percentages should add up to 100%.



The four power segments span a continuous area. Segment 1 lies underneath the gate, with its right edge aligned with the drain-side edge of the gate. The width can be extended to cover most (but not all) of the area under the gate. Segment 2 extends from the drain-side edge of the gate toward the drain. Segment 3 begins at the edge of segment 2, and segment 4 begins at the edge of segment 3. Segments 2-4 can be expanded to cover almost all of the area between the gate and drain. The widths are adjusted to smaller values when the gate-to-drain distance is reduced below their total.

The right edge of power segment 4 also serves to define the edge of the gate T metal (or field plate).

Power Cycle Parameters

The dissipated power (in W per mm of gate) is divided into two temporal components, the ON Power and the OFF Power. In a steady-state solution, the ON Power is dissipated continuously for all time. For a solution through time, the ON Power is dissipated for the ON Duration and then the OFF Power is dissipated for the OFF Duration. This ON/OFF power cycle is repeated until the solution completes. The Cycle Start parameter determines when in the power cycle the simulation will begin. A Cycle Start of zero means the simulation begins at the onset of the ON power level. The figure below depicts power levels for a 30% duty cycle starting in the ON segment.


For accurate simulations, the simulation time step should be much smaller than the ON or OFF power duration, because only the average power is dissipated for a time step in which a power switch occurs. See the section on Solutions Through Time for more information on setting the time step size for a simulation.

Note: When restarting a simulation from a previous solution file, the user must determine where in the power cycle to begin in order to continue the power cycle correctly. For example, if a simulation was originally carried out with ON Duration=25µs, OFF Duration=50µs, and Cycle Start=0, to restart the duty cycle from t=90µs the Cycle Start should be set to start 15µs into the second power cycle.

Materials

The generic FET includes a set of materials appropiate for a variety of HEMT/MESFET microwave device technologies. The materials and their data sources are described in detail in the Material Properties section of the Appendices.

Meshing

The number of finite elements generated for the thermal simulation can be controlled through the Meshing parameter list. A standard mesh gives excellent accuracy and runs much more quickly than a finer mesh. The standard mesh is recommended for all design analyses. A finer mesh, consisting of more finite elements, is selectable for verification of the accuracy of the standard mesh, if necessary. Use the Mesh Refinement parameter to change the number and density of mesh elements. A value of 1 (default) employs a standard mesh, while 2 gives a finer mesh.

Note: A thermal simulation with Mesh Refinement=2 can have millions of finite elements, and may take hours to run if the machine does not have many Gb of RAM. Simulations with larger numbers of gates and higher mesh refinements are only practical on 64-bit systems because of the limits on virtual memory in a 32-bit address space.

Layout Characteristics

The generic FET device can be incorporated in a layout. One reason to create a layout from such a device is to expand the boundaries to more realistic dimensions. The boundary ranges allowed by the device template are limited, but when incorporated into a layout the distances to the boundaries can be made as large as desired. The layers that are expanded to the boundaries of the layout are those of the Backside Adhesive, Metal Shim, Solder, and Substrate. The backside boundary conditions are also extended.

The generic FET can also be incorporated into a layout with multiple devices, and when this is done the default settings ensure that the materials used for the components Backside Adhesive, Metal Shim, Solder and Substrate are the same for all devices. The default settings also equalize the following parameter values across devices:

Backside Adhesive Thickness

Mesh Refinement

Metal Shim Thickness

Cycle Start

Solder Thickness

OFF Duration

Substrate Thickness

ON Duration

Source Via Metal

Backside Film Temperature


Backside Film Coefficient

The Source Via Metal thickness is equalized because it constrains the thickness of the top layer of the substrate which is a shared component. For more on why these parameters should remained equalized, see the Layout Templates section.

1For development of specific device templates contact SYMMIC_support@capesym.com

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